Technology which multi-layers an insulation substrate having IVH (inner via hole) structure while equipped with a conductive layer on one side has been proposed (for example, Japanese Patent Application Laid-Open No. HEI10-13028 and the like). This makes electric connection by connecting the conductive layer of one insulating base material with the via hole in the other insulating base material. Its function is exerted by mounting electric components such as IC chip and capacitor on a conductor circuit on an external layer appropriately. As a conventional art, Japanese Patent Application Laid-Open No. HEI10-13028 has been known.
FIG. 24 shows a printed wiring board for loading an IC chip according to a conventional art. FIG. 24(A) shows a plan view, and FIG. 24(B) shows a sectional view taken along the line B-B of FIG. 24(A). As shown in FIG. 24(B), a substrate 110 constituting a printed wiring board comprises a cavity 110a for accommodating an IC chip 170 and a via hole 118 for connecting the front face with the rear face. A rectangular bonding pad 136 is formed integrally on a land 118a of the via hole 118. A soldered bump 156 is connected to the rear face of the via hole 118 through a conductor circuit 138. The bonding pad 136 formed integrally with the via hole land 118a is projected from an opening 144 of soldered resist layer 140 so that its front end is exposed outside and wire-bonded with a terminal 171 of the IC chip 170 and wire 172.
Reduced thickness of film and intensified function of a substrate loaded with the IC chip have been demanded. The reason is that the casing of an electronic product such as portable phone, camera and personal computer has been reduced in size and thickness. To be accommodated in those casings, all the materials and components need to be thinned while keeping their function from dropping. Thus, constructing the IC chip in multi-layers so that its layers are stacked (in three dimensions) has been considered. According to the technology, an IC chip is loaded directly on an IC chip for multi-layer structure, that is, an upper IC chip is mounted on a lower IC chip by die bonding to stack layers. The layered IC chips are connected through the wire bonding. As a result, high density and small size can be achieved on the same area.
However, the substrate loaded with the layered IC chips cannot be repaired. Further, because connection is gained by wire bonding after the loading, the IC chip or the substrate cannot be inspected until the connection is gained by wire bonding. Thus, if there is even a single defect in the IC chip, the loaded substrate itself cannot be used.
Further, because no circuit is formed below the layered circuit or between IC chips, wiring cannot be placed around. Thus, with increase in clock number or the like, the wiring length prolongs. Upon a change in design or change in specification, appropriate formation by loading needs to be considered.
The present invention has been achieved to solve the above-described problems and an object of the invention is to provide a multi-layer printed wiring board which is easy to be multi-layered in terms of its structure and capable of withstanding changes in specification for design or the like.
Further, the board loaded with the IC chip has been demanded to have a higher wiring density. For this purpose, bonding pads for wire bonding need to be disposed in high density. However, because shown in FIG. 24(A), if the bonding pad 136 is formed integrally with a via hole land 118a, the via hole land 118a whose external shape is larger than the line width of the bonding pad 136 is disposed, the bonding pads cannot be disposed in high density.
The present invention has been achieved to solve the above-described problem and another object of the invention is to provide a multi-layer printed wiring board which enables the wiring density of the wire bonding to be intensified.